The performance advantages of III-V materials for many device applications have led to substantial interest in integrating these materials (and/or germanium (Ge)) with silicon (Si) technology. However, lattice mismatch issues can make it difficult to grow high quality, low defect III-V and Ge materials on Si substrates. A new approach, known as “aspect ratio trapping” (or ART) has been devised to overcome this problem. See, for example, J. Z. Li, et al., “Defect reduction of GaAs epitaxy on Si (001) using selective aspect ratio trapping,” Appl. Phys. Lett., vol. 91, Issue 2, 021114 (July 2007) (hereinafter “Li”). According to the process in Li, trenches are patterned (e.g., using reactive ion etching (RIE) through a patterned photoresist) in a layer over a crystalline substrate, and a III-V (or Ge) material is then selectively and epitaxially grown up from the trench bottoms to form fin shapes. The goal is that defects will get trapped by the trench sidewalls, and that the material in the upper portion of the fins will be defect free.
A concern with this approach, however, is that line-edge-roughness (LER) on the trench sidewalls (i.e., introduced by the lithographic patterning of the trenches—as a result of the photoresist roughness and/or the RIE process (RIE is a stochastic process that can induce sidewall roughness even if the photoresist had no LER)) will be exactly replicated in the III-V fins. LER on the sidewalls of fins used for FET devices is expected to reduce mobility (due to carrier scattering from the fin surfaces) and degrade threshold voltage control (due to variations in the fin width). In addition, LER on fins whose sidewalls are used as templates for subsequent epitaxial growth can introduce a distribution of exposed surface plane orientations which can lead to defective growth (since growth rate can depend on crystal orientation, leading to non-uniform and sometimes intersecting growth fronts). And finally, LER on the trench edges can potentially degrade the crystal quality of the grown fins if, for example, filling in the LER requires growth on non-favored crystal planes or if trench-edge asperities induce undesired spontaneous nucleation of III-V material that is supposed to grow epitaxially. An ART process can also be used with wider “fins” where the FET is made over the top surface of the wide “fin” as a planar device.
LER typically becomes more problematical as feature dimensions decrease. LER in an etched feature comes primarily from the LER replicated from the initial mask pattern, though additional random LER (unrelated to LER in the mask) can be introduced by the etching process used to transfer the pattern.
Given the ubiquity of LER and its potentially deleterious effects, it would be desirable to have techniques for making ART trenches and III-V fin structures with reduced LER. In particular, it would be desirable to have methods for making ART trenches and III-V fin structures with LER less than the LER introduced by the lithographic patterning.